Synchronous dynamic semiconductor memories with random access (SDRAM), and in particular SDRAM with double data rate (DDR-SDRAM), output, during reading out, their data (for which the abbreviation“DQ” is used) synchronously to a clock signal output by the memory. This clock signal, which is also referred to as data strobe and is usually abbreviated as “DQS”, in turn has to be synchronous to a clock signal (CLK) input externally in the memory. The external clock signal is generated by devices connected to the memory and communicating therewith and conveying the read instruction to the memory, the devices being, to facilitate matters, referred to as “system” in the following. The system may, for instance, include a processor. To the external clock signal CLK or the data strobe DQS, respectively, there are simultaneously generated respective complementary signals that are referred to as BCLK or BDQS, respectively. FIG. 1 shows, in a time flowchart, the external clock signal (CLK) with its complementary (BCLK), the data strobe with its complementary (BDQS), and the data signal (DQ) together with the synchronization between data strobe and data signal, and the synchronization between data strobe and external clock signal.
Known DDR-SDRAM memories comprise a device for synchronizing the data strobe generated from the external clock signal with the external clock signal, having, as a rule, a simple DLL-circuit (delay-locked-loop circuit). Such a circuit is, for instance, known from EP 964 517 and is illustrated in FIGS. 2 and 3.
The SDRAM chip illustrated in the top portion of FIG. 2 receives an external clock signal CLK as well as a complementary clock signal BCLK from a system. The clock signal received constitutes a differential clock signal and is converted to two single-ended clock signals via the receivers 1 and 2, wherein only the signal that is designated with CLK2DLL is looked at in FIG. 2 for reasons of clarity. The receiver delays the clock signal received by a predetermined delay time T1. By the DLL circuit 7 that is connected to the output of the receiver 1, the clock signal is delayed by a further variable delay time T2, so that the clock signal DCLK results. The clock signal DCLK is then delayed by a further delay time T3 via an off-chip-driver 4 positioned on the memory chip, and is then output from the memory chip to the system as data strobe during the reading out of data. A perfect synchronization between the external clock CLK and the data strobe DQS results when equation 1T1+T2+T3=n*Tp  (1)is fulfilled, where Tp is the clock period of an external clock signal and n is an integer that is larger than or equal to 1. The variable delay time T2 is adjusted by the DLL such that equation 1 is fulfilled, which is represented in the time flowcharts of the clock signals in FIG. 2 at the bottom.
FIG. 3 illustrates the detailed construction of the known DLL circuit 7 of FIG. 2. The known DLL circuit comprises a first delay unit 3 with a variably adjustable delay that receives the clock signal from the receiver and delays same by a variable time T2 and transfers it to the off-chip-driver. The DLL circuit moreover possesses a second delay unit 6 adjusted to a fixed desired delay time that corresponds approximately to the sum (T1f+T3f) of the delay T1 of the receiver and the delay T3 of the off-chip-driver. Due to this fed-back reference delay in the second delay unit, the DLL is capable of performing the clock synchronization. The output signal FBCLK of the second delay unit 6 is compared with respect to its phase in a phase detector 5 with the clock signal CLK2DLL output by the receiver. When there are differences with respect to the phasing between the signals CLK2DLL und FBCLK, the phase detector outputs a corresponding output signal to the first delay unit, this causing the delay time T2 to be corrected such that equation 1 is fulfilled. In a time flowchart in the lower portion of FIG. 3, how the signals FBCLK and CLK2DLL are first of all aligned with respect to one another for the DLL is illustrated, this resulting, later on, in the alignment between the signals CLK and DQS which is also represented in FIG. 3 at the bottom by a vertical line connecting corresponding states of the clock signals.
The quality of synchronization of these clock synchronization circuits known in prior art substantially depends on the exactness of the fixed desired delay time of the second delay unit. A relatively good synchronization can be achieved when simply copies of the receiver and of the off-chip-driver are connected in series as delay elements in the second delay unit. This solution is, however, not advantageous since it requires a large layout region and, moreover, necessitates a great deal of current. An alternative solution with low current consumption and little requirement of layout region would be an inverter chain which, however, has the disadvantage that it is highly dependent on the semiconductor manufacturing process and on fluctuations in voltage supply result, so that this solution is also not ideal.
There are, however, further important disadvantages with the devices for synchronizing clock signals known in prior art and described above. Thus, for instance, fluctuations in the supply voltage of the receiver or of the off-chip-driver will add additional deviations to the delay times of these devices. What is most problematical is, however, the fact that the dependency of the time delay T3 on the capacitive and/or ohm resistive load available at the output of the SDRAM chip, which can differ depending on the respective use of the chip, cannot be taken into account in the DLL control circuit. Varying casings of the chip which may have an influence on the delay times cannot be taken into account, either.
The negative effect that the described fluctuations of the delay times of the individual devices, which are important for the determination of the total delay time resulting in accordance with equation 1, can have is illustrated in FIG. 4, where the data strobe DQS can no longer be aligned to the external clock signal CLK. Due to the fluctuations of the delay times, the fixedly adjusted delay time Tf of the second delay unit 8 does no longer corresponds to the sum of the delay times T1 and T3 that are actually introduced by the receiver or the off-chip-driver, respectively.
By means of such deviations in time, the time window for reading out the data, the so-called data eye, which is created by the overlapping of corresponding logic states of data strobe and data signal, becomes smaller, and a reliable reading out of the data from the memory chip to the system may become impossible. This particularly has an effect with memories with double data rate (DDR) where one data bit is addressed with the rising clock edge and one with the falling clock edge.